A deep trench isolation structure is typically formed to provide isolation between adjacent active regions of a semiconductor substrate. For example, in a typical Bipolar Complementary-Metal-Oxide-Semiconductor (BiCMOS) process, a deep trench isolation structure may electrically isolate a bipolar transistor from an adjacent Complementary-Metal-Oxide-Semiconductor (CMOS) transistor fabricated on the same semiconductor substrate.
In a conventional deep trench isolation process flow, a plurality of undesirable deep mini-trenches or cavities may be formed on the edges of the silicon substrate. As a result, the integrated circuit devices formed on the substrate may likely suffer from scratch defects due to the undesirable abrasions during a subsequent planarization process.
Therefore, there is a need of providing an improved a method for fabricating the deep trench isolation regions to obviate the drawbacks encountered from the prior art.